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mpi/alpha/README
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EV4 | EV4 | ||||
1. This chip has very limited store bandwidth. The on-chip L1 cache is | 1. This chip has very limited store bandwidth. The on-chip L1 cache is | ||||
write-through, and a cache line is transfered from the store buffer to the | write-through, and a cache line is transferred from the store buffer to the | ||||
off-chip L2 in as much 15 cycles on most systems. This delay hurts | off-chip L2 in as much 15 cycles on most systems. This delay hurts | ||||
mpn_add_n, mpn_sub_n, mpn_lshift, and mpn_rshift. | mpn_add_n, mpn_sub_n, mpn_lshift, and mpn_rshift. | ||||
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1. The memory bandwidth of this chip seems excellent, both for loads and | 1. The memory bandwidth of this chip seems excellent, both for loads and | ||||
stores. Even when the working set is larger than the on-chip L1 and L2 | stores. Even when the working set is larger than the on-chip L1 and L2 | ||||
caches, the perfromance remain almost unaffected. | caches, the performance remain almost unaffected. | ||||
2. mulq has a measured latency of 13 cycles and an issue rate of 1 each 8th | 2. mulq has a measured latency of 13 cycles and an issue rate of 1 each 8th | ||||
cycle. umulh has a measured latency of 15 cycles and an issue rate of 1 | cycle. umulh has a measured latency of 15 cycles and an issue rate of 1 | ||||
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