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cipher/sha512.c

Context not available.
#include "g10lib.h" #include "g10lib.h"
#include "bithelp.h" #include "bithelp.h"
#include "bufhelp.h" #include "bufhelp.h"
#include "cipher.h" #include "cipher.h"
#include "hash-common.h" #include "hash-common.h"
#include "sha2-common.h"
/* USE_ARM_NEON_ASM indicates whether to enable ARM NEON assembly code. */
#undef USE_ARM_NEON_ASM
#ifdef ENABLE_NEON_SUPPORT
# if defined(HAVE_ARM_ARCH_V6) && defined(__ARMEL__) \
&& defined(HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS) \
&& defined(HAVE_GCC_INLINE_ASM_NEON)
# define USE_ARM_NEON_ASM 1
# endif
#endif /*ENABLE_NEON_SUPPORT*/
/* USE_ARM_ASM indicates whether to enable ARM assembly code. */
#undef USE_ARM_ASM
#if defined(__ARMEL__) && defined(HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS)
# define USE_ARM_ASM 1
#endif
/* USE_SSSE3 indicates whether to compile with Intel SSSE3 code. */
#undef USE_SSSE3
#if defined(__x86_64__) && defined(HAVE_GCC_INLINE_ASM_SSSE3) && \
defined(HAVE_INTEL_SYNTAX_PLATFORM_AS) && \
(defined(HAVE_COMPATIBLE_GCC_AMD64_PLATFORM_AS) || \
defined(HAVE_COMPATIBLE_GCC_WIN64_PLATFORM_AS))
# define USE_SSSE3 1
#endif
/* USE_AVX indicates whether to compile with Intel AVX code. */
#undef USE_AVX
#if defined(__x86_64__) && defined(HAVE_GCC_INLINE_ASM_AVX) && \
defined(HAVE_INTEL_SYNTAX_PLATFORM_AS) && \
(defined(HAVE_COMPATIBLE_GCC_AMD64_PLATFORM_AS) || \
defined(HAVE_COMPATIBLE_GCC_WIN64_PLATFORM_AS))
# define USE_AVX 1
#endif
/* USE_AVX2 indicates whether to compile with Intel AVX2/rorx code. */
#undef USE_AVX2
#if defined(__x86_64__) && defined(HAVE_GCC_INLINE_ASM_AVX2) && \
defined(HAVE_GCC_INLINE_ASM_BMI2) && \
defined(HAVE_INTEL_SYNTAX_PLATFORM_AS) && \
(defined(HAVE_COMPATIBLE_GCC_AMD64_PLATFORM_AS) || \
defined(HAVE_COMPATIBLE_GCC_WIN64_PLATFORM_AS))
# define USE_AVX2 1
#endif
typedef struct typedef struct
{ {
u64 h0, h1, h2, h3, h4, h5, h6, h7; u64 h0, h1, h2, h3, h4, h5, h6, h7;
Context not available.
U64_C(0x3c9ebe0a15c9bebc), U64_C(0x431d67c49c100d4c), U64_C(0x3c9ebe0a15c9bebc), U64_C(0x431d67c49c100d4c),
U64_C(0x4cc5d4becb3e42b6), U64_C(0x597f299cfc657e2a), U64_C(0x4cc5d4becb3e42b6), U64_C(0x597f299cfc657e2a),
U64_C(0x5fcb6fab3ad6faec), U64_C(0x6c44198c4a475817) U64_C(0x5fcb6fab3ad6faec), U64_C(0x6c44198c4a475817)
}; };
/* AMD64 assembly implementations use SystemV ABI, ABI conversion and additional
* stack to store XMM6-XMM15 needed on Win64. */
#undef ASM_FUNC_ABI
#undef ASM_EXTRA_STACK
#if defined(USE_SSSE3) || defined(USE_AVX) || defined(USE_AVX2)
# ifdef HAVE_COMPATIBLE_GCC_WIN64_PLATFORM_AS
# define ASM_FUNC_ABI __attribute__((sysv_abi))
# define ASM_EXTRA_STACK (10 * 16 + 4 * sizeof(void *))
# else
# define ASM_FUNC_ABI
# define ASM_EXTRA_STACK 0
# endif
#endif
#ifdef USE_ARM_NEON_ASM #ifdef USE_ARM_NEON_ASM
unsigned int _gcry_sha512_transform_armv7_neon (SHA512_STATE *hd, unsigned int _gcry_sha512_transform_armv7_neon (SHA512_STATE *hd,
const unsigned char *data, const unsigned char *data,
const u64 k[], size_t num_blks); const u64 k[], size_t num_blks);
Context not available.
SHA512_CONTEXT *hd = ctx; SHA512_CONTEXT *hd = ctx;
return _gcry_sha512_transform_armv7_neon (&hd->state, data, k, nblks); return _gcry_sha512_transform_armv7_neon (&hd->state, data, k, nblks);
} }
#endif #endif
#ifdef USE_PPC_ASM
void sha512_block_p8 (SHA512_STATE *hd,
const unsigned char *data,
size_t len);
static unsigned int
do_sha512_transform_ppc8 (void *ctx, const unsigned char *data,
size_t nblks)
{
SHA512_CONTEXT *hd = ctx;
sha512_block_p8 (&hd->state, data, nblks);
return 128; /* uses 128 bytes of stack space */
}
#endif
#ifdef USE_SSSE3 #ifdef USE_SSSE3
unsigned int _gcry_sha512_transform_amd64_ssse3(const void *input_data, unsigned int _gcry_sha512_transform_amd64_ssse3(const void *input_data,
void *state, void *state,
size_t num_blks) ASM_FUNC_ABI; size_t num_blks) ASM_FUNC_ABI;
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ctx->bctx.bwrite = do_transform_generic; ctx->bctx.bwrite = do_transform_generic;
#ifdef USE_ARM_NEON_ASM #ifdef USE_ARM_NEON_ASM
if ((features & HWF_ARM_NEON) != 0) if ((features & HWF_ARM_NEON) != 0)
ctx->bctx.bwrite = do_sha512_transform_armv7_neon; ctx->bctx.bwrite = do_sha512_transform_armv7_neon;
#endif #endif
#ifdef USE_PPC_ASM
if ((features & HWF_PPC_VCRYPTO) != 0)
ctx->bctx.bwrite = do_sha512_transform_ppc8;
#endif
#ifdef USE_SSSE3 #ifdef USE_SSSE3
if ((features & HWF_INTEL_SSSE3) != 0) if ((features & HWF_INTEL_SSSE3) != 0)
ctx->bctx.bwrite = do_sha512_transform_amd64_ssse3; ctx->bctx.bwrite = do_sha512_transform_amd64_ssse3;
#endif #endif
#ifdef USE_AVX #ifdef USE_AVX
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