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Speed-up SHA-1 NEON assembly implementation
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Description

Speed-up SHA-1 NEON assembly implementation

* cipher/sha1-armv7-neon.S: Tweak implementation for speed-up.

Benchmark on Cortex-A8 1008Mhz:

New:

|  nanosecs/byte   mebibytes/sec   cycles/byte

SHA1 | 7.04 ns/B 135.4 MiB/s 7.10 c/B

Old:

|  nanosecs/byte   mebibytes/sec   cycles/byte

SHA1 | 7.79 ns/B 122.4 MiB/s 7.85 c/B

  • Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>

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jukiviliAuthored on Jun 29 2014, 4:36 PM
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rC066f068bd0bc: gostr3411_94: rewrite to use u32 mathematic
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Jussi Kivilinna <jussi.kivilinna@iki.fi> committed rC1b9b00bbe41b: Speed-up SHA-1 NEON assembly implementation (authored by Jussi Kivilinna <jussi.kivilinna@iki.fi>).Jun 29 2014, 4:36 PM

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